User`s guide

A.3 PCI Dense Memory Space

A.3.3 Flash ROM Conﬁguration Registers

Table A–10 lists the conﬁguration registers for the Intel 28F008SA 1MB ﬂash

ROM. A read operation is performed by reading from the appropriate address.

To write data, the ﬂash ROM must ﬁrst be erased. The structure of the

ﬂash ROM allows only the ﬂash ROM to be erased in 64KB blocks (see

Section A.3.2).

In order to change one byte, the following steps must be completed:

1. Read the entire 64KB block into system memory.

2. Change the desired byte in system memory.

3. Erase the 64KB block in ﬂash ROM.

4. Write the entire 64KB block from system memory to the ﬂash ROM.

Note

In order to write to ﬂash ROM, Jumper J14 (protect/enable) must be

positioned on pins 2 and 3 (see Table 2–1 and schematic eb164.33).

All ﬂash ROM accesses (except for read operations) require two bus cycles.

During the ﬁrst cycle, register data is written to set up the registers. During

the second cycle, the read or write transaction performs the operation desired.

For more information about reading, erasing, and writing the ﬂash ROM, see

the Intel Flash Memory document.

Accessing the ﬂash ROM registers requires byte access, which is only possible

through use of PCI sparse memory space. The EB164 ﬂash ROM resides in

PCI memory address range FFF8.0000 to FFFF.FFFF. See Section 4.2.2 for

information about accessing this address range through sparse memory space.

A–14 I/O Space Address Maps