User`s guide

A.2 PCI Sparse I/O Space
A.2.1.5 Configuration Jumpers (CONF4—CONF15)
Reading the addresses listed in Table A–5 returns the value of the
configuration jumpers CONF4 through CONF15. Bits corresponding to CONF0
through CONF3 are hardwired to the presence detect signals from the DRAM
SIMMs.
Table A–5 Configuration Jumpers (CONF4—CONF15)
Offset Physical Address Description
x801 85.8001.0020 Bits <3:0> are presence detect signals
<PD4:PD1>. Bits <7:4> are CONF<7:4>.
x802 85.8001.0040 Bits <7:0> are CONF<15:8>.
A.2.1.6 Interrupt Control PLD Addresses
Table A–6 lists the registers and memory addresses for the interrupt control
programmable logic device (PLD).
Table A–6 Interrupt Control PLD Addresses
Offset Physical Address Register
x804 85.8001.0080 Interrupt status/interrupt mask 1
x805 85.8001.00A0 Interrupt status/interrupt mask 2
x806 85.8001.00C0 Interrupt status/interrupt mask 3
A.2.2 PCI Sparse I/O Space—Region B
PCI sparse I/O space—region B—occupies physical addresses 85.C000.0000
through 85.FFFF.FFFF. This region includes the PCI-to-ISA bridge operating
register address space as well as the operating registers for any optional PCI
plug-in boards. Table A–7 is a map of the SIO PCI-to-ISA bridge operating
address space.
A–8 I/O Space Address Maps