Specifications

Chapter 3. Theory of Operation

ETHERNET: DEC21140A

The Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller chip supports the peripheral

component interconnect (PCI) bus. Some of the DEC21140A's features are listed below. This list is

followed by two topics providing outlines of the DEC21140A's configuration registers and command

and status registers (CSRs).

For more detailed information about the DEC21140A, refer to the DEC21140A data book, available

from Digital Equipment Corporation at 1-800-332-2717.

• Supports either 10 Mbits/s or 100 Mbits/s network ports

• Provides a standard 10 Mbits/s and 100 Mbits/s MII supporting CAT 5 UTP and shielded twisted-

pair (STP) cables

• Contains onchip scrambler and PCS for CAT 5 to significantly reduce the cost of 100BASE-T

solutions

• Supports full-duplex operation on both 10 Mbits/s and 100 Mbits/s ports

• Provides internal loopback capability on both ports

• Contains a variety of flexible address filtering modes (including perfect, hash table, inverse perfect,

and promiscuous):

-- 16 perfect addresses (normal or inverse filtering)

-- 512 hash-filtered addresses

-- 512 hash-filtered multicast addresses and one perfect address

-- Pass all multicast

• Contains large independent receive and transmit FIFOs; no additional onboard memory required

• Supports either big or little endian byte ordering for buffers and descriptors

• Supports IEEE 802.3, ANSI 8802-3, and Ethernet standards

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