User`s manual

Jumpers (cont’d)
flash ROM, 2–6
L2 cache address, 2–6
MINI_DEBUG, 2–4
sp_bit6, 2–4
sp_bit7, 2–4
sp_bit<2:0>, 2–5
sp_bit<5:3>, 2–4
K
Key lock connector, 2–13
Keyboard connector, 2–9
Keyboard controller, 1–5
L
L2 cache
address jumper, 2–6
SIMM slots, 2–9
subsystem, 1–4
Level 2 cache
See L2 cache
M
Memory subsystem, 1–1
See DRAM
MINI_DEBUG jumper, 2–4
Mouse connector, 2–9
Mouse controller, 1–5
O
Operating Systems
See OS
OS
software support, 1–6
P
PAL control set, 1–4
Parallel interface, 1–5
Parallel port connector, 2–10
Parameters, 5–1, 5–2
PCI
arbitration, 4–1, 4–5
arbitration logic, 4–1
interface overview, 1–5
interrupt logic, 4–1
slots, 2–9
Peripheral component interconnect
See PCI
Physical board parameters, 5–2
Power connectors, 2–11
Power distribution, 4–5
Power LED connector, 2–13
Power requirements, 5–1
See also Power distribution
R
RAM
See DRAM; SRAM
Registers
interrupt mask, 4–4
ROM
See Flash ROM
See Flash ROM; SROM
S
Saturn IO chip
See SIO chip
Serial interface, 1–5
Serial ROM
See SROM, code; SROM, test connector
SIMM
bank layouts, 1–1, 1–2
DRAM, 1–1
SRAM, 1–4
Single inline memory module
See SIMM
SIO chip, 1–5, 4–1
interrupt logic, 4–1
Index–3