User`s manual

CPU clock divisor jumpers, 2–7
CPU fan connector, 2–12
D
dc power distribution, 4–5
See also Power requirements
Debug monitor, 3–5
code in flash ROM, 1–6
starting, 3–6
Debugging
native, 1–6
source-level, 1–6
DECchip 21071-BA, 1–4
DECchip 21071-CA, 1–4
DECchip 21071-DA, 1–4
DECchip 21072 chipset, 1–1, 1–4
DECladebug, 1–6
Disk access LED connector, 2–13
Diskette controller, 1–5
Diskette drive
connector, 2–10
DRAM, 1–1
SIMM connectors, 2–10
Dynamic RAM
See DRAM
E
Enclosure fan connector, 2–13
Environmental characteristics, 5–2
F
Fan connectors
CPU, 2–12
enclosure, 2–13
Features, 1–1
Flash ROM, 4–6
access, 4–11
address bit 19, 4–11
enable/disable jumpers, 2–6
header content, 4–6, 4–8
higher bank image selection, 4–10
jumper, 2–6
Flash ROM (cont’d)
special headers, 4–6
structure, 4–9
TOY RAM location 3F, 4–10
update-enable jumper, 4–12
Floppy drive
See Diskette drive
H
Hardware configuration jumpers, 2–6
Hardware requirements, 3–1 to 3–2
I
I/O chip
See SIO chip
IDE, 1–5
connector, 2–10
Industry Standard Architecture
See ISA
Integrated device electronics
See IDE
Interrupt
assignment, 4–3
control, 4–1
mask registers, 4–4
scheme, 4–1
sources, 4–3
Interrupt control and PCI arbitration logic
block diagram, 4–1
ISA
arbitration, 4–5
devices, 4–5
interface overview, 1–5
slots, 2–9
J
Jumpers
BC_SIZE<2:0>, 2–5
BC_SPEED<2:0>, 2–4
BOOT_OPTION, 2–4
configuration, 2–1 to 2–7
CPU clock divisor, 2–7
Index–2