User`s manual

Index
A
Arbitration
PCI, 4–1
scheme, 4–5
B
Backup cache
See L2 cache
Bank selection
flash ROM, 4–10
BC_SIZE<2:0> jumpers, 2–5
BC_SPEED<2:0> jumpers, 2–4
Block diagram
board, 1–1
interrupt control and PCI arbitration
logic, 4–1
Board
configuration, 2–1
connectors, 2–7, 2–9
overview, 1–1
parameters, 5–1, 5–2
Board block diagram, 1–1
Board components, 1–1
Board features, 1–1
Board interrupts, 4–1
Board reset connector, 2–13
BOOT_OPTION jumper, 2–4
Bridge
See SIO chip
C
Cache
See L2 cache
Chipset support, 1–4
Clock subsystem overview, 1–5
COM1 connector, 2–10
COM2 connector, 2–10
Components, 1–1
Configuration, 2–1
hardware, 3–2
software, 3–5
Connectors, 2–7 to 2–13
board reset, 2–13
COM1, 2–10
COM2, 2–10
CPU fan, 2–12
disk access LED, 2–13
DRAM SIMM, 2–10
Enclosure fan, 2–13
IDE, 2–10
key lock, 2–13
keyboard, 2–9
mouse, 2–9
parallel port, 2–10
power, 2–11
power LED, 2–13
speaker, 2–13
SROM test, 2–10
Console interface
code in flash ROM, 1–6
Conventions, viii
Index–1