User`s manual

4.1 PCI Interrupts and Arbitration
Interrupt Level Interrupt Source
IRQ9, IRQ10,
IRQ11
16-bit ISA
IRQ12 Mouse
IRQ13 16-bit ISA
IRQ14 IDE
IRQ15 16-bit ISA
The Alpha PCI 64–275 timer interrupt is generated by the real-time clock by
means of cpu_irq1, rather than by the timer within the SIO, which would
route the interrupt through the ISA bus interrupts.
Interrupt PLDs Function
The MACH210 PLD acts as an 8-bit I/O slave on the ISA bus at addresses
804h, 805h, and 806h. This is accomplished by a decode of the three ISA
address bits sa<2:0> and the three ecas_addr<2:0> bits.
Each interrupt can be individually masked by setting the appropriate bit in the
mask register. An interrupt is disabled by writing a 1 to the desired position
in the mask register. An interrupt is enabled by writing a 0. For example,
bit <7> set in interrupt mask register 1 indicates that the INTB2 interrupt is
disabled. There are three mask registers located at ISA addresses 804h, 805h,
and 806h.
An I/O read transaction at ISA addresses 804h, 805h, and 806h returns the
state of the 17 PCI interrupts rather than the state of the masked interrupts.
On read transactions, a 1 means that the interrupt source shown in Figure 4–2
has asserted its interrupt. The mask register can be updated by writing
addresses 804h, 805h, or 806h. The mask register is write-only.
4–4 Functional Elements