User`s guide

The address generation in dense space is as follows:

• Bits sysBus<31:5> are sent out on ad<31:5>.

• On read transactions, ad<4:3> is generated from cpucwmask<1:0>;

ad<2> is always 0.

• On write transactions, ad<4:2> is generated from cpucwmask<7:0>.If

the lower longword is to be written, ad<2> is 0; if the lower longword

is masked out and the upper longword is to be written, ad<2> is 1.

The number of longwords written on the PCI is directly obtained from

cpucwmask<7:0>. Any combination of cpucwmask<7:0> is allowed by

the 21072 chipset.

Note

If the cache line written by the processor has holes, that is, if some

of the longwords are masked out, the corresponding transfer is still

performed on the PCI with disabled byte enables. Downstream bridges

must be able to deal with disabled byte enables on the PCI during

write transactions.

4.2 PCI-to-Physical Memory Addressing

Incoming 32-bit memory addresses are mapped to the 34-bit physical memory

addresses. The 21071-DA allows two regions in PCI memory space to be

mapped to system memory with two programmable address windows. The

mapping from the PCI address to the physical address can be direct (physical

mapping with an extension register) or scatter-gather mapped (virtual). These

two address windows are referred to as the PCI target windows.

Each window has three registers associated with it: PCI base register, PCI

mask register, and the translated base register. Appendix A contains the

The PCI mask register provides a mask corresponding to ad<31:20> of an

incoming PCI address. The size of each window can be programmed from 1MB

to 4GB (in powers of 2) by masking bits of the incoming PCI address, using the

PCI mask register as speciﬁed in Table 4–8.

System Address Mapping 4–19