User`s guide

Table 4–7 PCI Sparse Memory Space Byte Enable Generation
Length
CPU
Address<6:5>
CPU
Address<4:3>
PCI Byte
Enable
1
PCI ad<2:0>
2
Byte 00 00 1110 CPU address<7>, 00
01 00 1101 CPU address<7>, 00
10 00 1011 CPU address<7>, 00
11 00 0111 CPU address<7>, 00
Word 00 01 1100 CPU address<7>, 00
01 01 1001 CPU address<7>, 00
10 01 0011 CPU address<7>, 00
11 01 Illegal
3
—
Tribyte 00 10 1000 CPU address<7>, 00
01 10 0001 CPU address<7>, 00
10 10 Illegal
3
—
11 10 Illegal
3
—
Longword 00 11 0000 CPU address<7>, 00
Longword 01 11 Illegal
3
—
Longword 10 11 Illegal
3
—
Quadword 11 11 0000 000
1
Byte enable set to 0 indicates that byte lane carries meaningful data.
2
In PCI sparse memory space, PCI ad<1:0> are always 00.
3
These combinations are architecturally illegal. If there is an access with this combination
of address<6:3>, the 21071-DA will respond to the transactions but the results are
UNPREDICTABLE.
On write transactions, the relationship between cpucwmask<7:0> and
sysBus<4:3> is as follows:
If cpucwmask<1:0> is nonzero, sysBus<4:3> is 00.
If cpucwmask<3:2> is nonzero, sysBus<4:3> is 01.
If cpucwmask<5:4> is nonzero, sysBus<4:3> is 10.
If cpucwmask<7:6> is nonzero, sysBus<4:3> is 11.
System Address Mapping 4–17