User`s guide

If the bus number of the conﬁguration cycle matches the bus number of the

bridge chip secondary PCI interface, it will intercept the conﬁguration cycle,

decode it, and generate a PCI conﬁguration cycle with ad<1:0> equal to 01

on its secondary PCI interface. If the bus number is within the range of bus

numbers that may exist hierarchically behind its secondary PCI interface, the

PCI conﬁguration cycle passes, unmodiﬁed (leaving ad<1:0> = 01), through

the bridge. The conﬁguration cycle will be intercepted and decoded by a

downstream bridge.

4.1.8 PCI Sparse Memory Space (2 0000 0000 to 2 FFFF FFFF)

Access to PCI sparse memory space can have byte, word, tribyte, longword, or

quadword granularity. The Alpha architecture does not provide byte, word, or

tribyte granularity, which the PCI requires. To provide this granularity, the

byte enable and byte length information is encoded in the lower address bits of

this space (ad<7:3>).

Bits sysBus<31:8> generate quadword addresses on the PCI, resulting in a

sparse 4GB space that maps to 128MB of PCI address space. An access to this

space causes a memory read or write access on the PCI.

Bits sysBus<33:32> identify the various address spaces on the sysBus. Bits

sysBus<7:3> generate the length of the PCI transaction in bytes, the byte

enables, and ad<2:0> (see Table 4–7). Bits sysBus<31:8> correspond to the

quadword PCI addresses and are sent out on ad<26:3> during the address

phase on the PCI.

Bits ad<31:27> are obtained from one of two host address extension registers

(HAXR0 and HAXR1). HAXR0 (which is hardcoded as 0) is used for sysBus

addresses from 2 0000 0000 to 2 1FFF FFFF (that is, when sysBus<31:29>

is 0). The HAXR1 register maps sysBus addresses from 2 2000 0000 to

2 FFFF FFFF (that is, when sysBus<31:29> is nonzero anywhere in the PCI

address space).

HAXR1 is a CSR in the 21071-DA and is fully programmable. This allows

ISA devices that require memory to be mapped in the lower 16MB to coexist

with other devices that do not have that restriction. The lower 16MB have a

ﬁxed mapping (HAXR0) to 0, and the remaining 112MB can be programmed

anywhere in PCI space.

System Address Mapping 4–15