User`s guide

4–5 SG Map Page Table Entry in Memory .................. 4–23
4–6 SG Map Translation of PCI to SysBus Address . .......... 4–25
5–1 Major Board Component Layout . . . ................... 5–3
A–1 General Control Register . ........................... A–2
A–2 Error and Diagnostic Status Register .................. A–4
A–3 Tag Enable Register ................................ A–6
A–4 Error Low Address Register .......................... A–8
A–5 Error High Address Register ......................... A–9
A–6 LDx_L Low Address Register ......................... A–9
A–7 LDx_L High Address Register ........................ A–9
A–8 Video Frame Pointer Register ........................ A–10
A–9 Presence Detect Low-Data Register . ................... A–11
A–10 Presence Detect High-Data Register ................... A–12
A–11 Bank Set 0 Base Address Register . . ................... A–12
A–12 Bank Set 0 to 7 Configuration Register ................. A–14
A–13 Bank Set 8 Configuration Register. . ................... A–16
A–14 Bank Set Timing Register A ......................... A–18
A–15 Bank Set Timing Register B ......................... A–20
A–16 Global Timing Register . . ........................... A–22
A–17 Refresh Timing Register . ........................... A–23
A–18 Diagnostic Control and Status Register ................. A–25
A–19 sysBus Error Address Register ....................... A–29
A–20 PCI Error Address Register .......................... A–30
A–21 Translated Base Registers 1 and 2 . . ................... A–31
A–22 PCI Base Registers 1 and 2 .......................... A–32
A–23 PCI Mask Registers 1 and 2 ......................... A–33
A–24 Host Address Extension Register 0 . ................... A–34
A–25 Host Address Extension Register 1 . ................... A–34
A–26 Host Address Extension Register 2 . ................... A–35
A–27 PCI Master Latency Timer Register. ................... A–36
A–28 TLB Tag Registers 0 Through 7 ....................... A–37
A–29 TLB Data Registers 0 Through 7 . . . ................... A–38
B–1 Write Cycle Timing ................................ B–7
B–2 Special Header Content . . ........................... B–10
B–3 J3 Connector (Repeated) . ........................... B–17
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