User`s guide

4.1.6 PCI Sparse I/O Space (1 C000 0000 to 1 DFFF FFFF)
The PCI sparse I/O space is similar to the PCI sparse memory space. This
512MB sysBus address space maps to 16MB of PCI I/O address space. A
read or write transaction to this space causes a PCI I/O read or PCI I/O write
command respectively.
Bits sysBus<33:29> identify the various address spaces on the sysBus. Bits
sysBus<6:3> generate the length of the PCI transaction in bytes, the byte
enables, and ad<2:0> on the PCI (see Table 4–4).
Bits sysBus<28:8> correspond to the quadword PCI addresses and are sent
out on ad<23:3> during the address phase on the PCI. Bits ad<31:24>
are obtained from one of two host address extension registers (HAXR0
and HAXR2). The HAXR0 register (which is hardcoded as 0) is used for
sysBus addresses between 1 C000 0000 and 1 C07F FFFF (that is, when
sysBus<28:23> are 0).
The HAXR2 register maps sysBus addresses between 1 C080 0000 and
1 DFFF FFFF (that is, when sysBus<28:23> are nonzero anywhere in the
PCI address space). The HAXR2 register is a CSR in the 21071-DA chip and
is fully programmable. This allows ISA devices that require their I/O space
to be in the lower 256KB to coexist with other devices that do not have that
restriction. The lower 256KB of I/O space have fixed mapping (HAXR0 to
0), and the remaining I/O space (64MB minus 64KB) can be programmed
anywhere in PCI space.
Figure 4–2 shows the sysBus-to-PCI I/O address translation. Table 4–4 shows
how the byte enable bits and PCI ad<2:0> are generated from sysBus<6:3>.
System Address Mapping 4–9