User`s guide

Table 4–3 (Cont.) DECchip 21071-DA CSR Register Addresses

Address

1 A000 0300 TLB 0 data register

1 A000 0320 TLB 1 data register

1 A000 0340 TLB 2 data register

1 A000 0360 TLB 3 data register

1 A000 0380 TLB 4 data register

1 A000 03A0 TLB 5 data register

1 A000 03C0 TLB 6 data register

1 A000 03E0 TLB 7 data register

1 A000 0400 Translation buffer invalidate all register (TBIA)

4.1.5 PCI Interrupt Acknowledge/Special Cycle Space (1 B000 0000 to

1 BFFF FFFF)

A read access to this space causes an interrupt acknowledge cycle on the

PCI. Bits sysBus<6:3> are used to generate the byte enables on the PCI as

speciﬁed in Table 4–4. Bits sysBus<26:7> are in a don’t care state during this

transaction.

A write access to this space causes a special cycle on the PCI. The address and

byte enables are in a don’t care state during this transaction.

Note

Software must use an STL instruction to initiate these transactions.

An STQ instruction will result in a 2-longword burst on the PCI, which

is illegal.

4–8 System Address Mapping