User`s guide

Table 4–1 (Cont.) sysBus Address Space Description
sysAdr
<33:32>
sysAdr
<31:28> Address Space Description
01 xxxx PCI sparse memory
space
128MB addressable PCI space.
The lower address bits are used
to determine byte masks and
transaction length information. The
4GB space is reduced to a 128MB
sparse space. Use this space when
byte or word granularity is required.
Read or write length is no more
than a quadword. Reading other
than the requested data is harmful.
Prefetching read data is prohibited.
Dstream access only.
11 xxxx PCI dense memory
space
4GB of PCI space. Used for devices
with access granularity greater than
one longword. Read transactions do
not have side effects; prefetching data
from PCI devices is allowed. Typically
used for data buffers. Dstream access
only.
4.1.1 Cacheable Memory Space (0 0000 0000 to 0 FFFF FFFF)
The 21071-CA recognizes the 4GB of quadrant 0 (corresponding to
sysBus<33:32> = 00) as cacheable memory space. The 21071-CA responds
to all read and write accesses in this space. Some or all of main memory can
be programmed to be in cacheable space.
4.1.2 Noncacheable Memory Space (1 0000 0000 to 1 7FFF FFFF)
The 21071-CA recognizes the lower 2GB of quadrant 1 (corresponding to
sysBus<33:32> = 01) as noncacheable memory space. The L2 cache is
bypassed by the 21071-CA on accesses to this space. Some or all of main
memory can be programmed to be in this space. If a frame buffer is supported
in system memory, it should be addressed in this space.
4–4 System Address Mapping