User`s guide

Table 4–1 sysBus Address Space Description
sysAdr
<33:32>
sysAdr
<31:28> Address Space Description
00 xxxx Cacheable memory
space
Accessed by the CPU instruction
stream (Istream) or data stream
(Dstream). Accessed by DMA.
The 21071-DA does not respond to
addresses in this space.
01 0xxx Noncacheable
memory space
Accessed by the CPU (Istream or
Dstream). Accessed by DMA. Can be
used for a frame buffer on the DRAM
bus.
The 21071-DA does not respond to
addresses in this space.
01 100x 21071-CA CSRs The 21071-CA responds to all
addresses in this space. Dstream
access only.
The 21071-DA does not respond to
addresses in this space.
01 1010 21071-DA CSRs The 21071-DA responds to all
addresses in this space. Dstream
access only.
01 1011 PCI interrupt
acknowledge or
PCI special cycle
The 21071-CA expects the 21071-DA
to respond to all addresses in this
space.
A read transaction causes a PCI
interrupt acknowledge; a write
transaction causes a special cycle.
Dstream access only.
01 110x PCI sparse I/O space 16MB of PCI space. The lower
256KB of this space must be used for
addressing the PCI and ISA devices.
The remainder of the space can be
used for other devices. Dstream
access only.
01 111x PCI configuration
space
A read or write transaction to this
address space causes a configuration
read or write cycle on the PCI.
Dstream access only.
(continued on next page)
System Address Mapping 4–3