User`s guide

A TL7702B power monitor senses the +3-V dc input to ensure that it is stable

before the 21064A inputs and I/O pins are driven. Any device that drives the

21064A has a tristate output controlled by the power monitor output.

If the +3-V dc output fails, the power monitor enables sense_dis, which is

applied to the reset logic (AlphaPC64.36). The reset logic generates a group of

reset functions to the 21064A and the remainder of the system, including PCI

devices (see Section 3.12).

3.12 Reset and Initialization

An external switch can be connected to J3 (AlphaPC64.4) to control the reset

signal (see Figure 3–16). The external switch state is ORed with p_dcok,

from the external power supply and with fan_ok_l to assert pre_reset. The

pre_reset function initializes the 21064A and the system logic, but does not

send an initialization pulse to the ISA devices.

If either p_dcok or fan_ok_l is deasserted, it will cause pre_reset to be

asserted and b_dcok to be deasserted. Asserting b_dcok causes a full system

initialization, equivalent to a power-down and power-up cycle.

3.13 System Software

The AlphaPC64 software is divided into the following categories:

• Serial ROM code

• Flash ROM code

• Operating systems

3.13.1 Serial ROM Code

The serial ROM code is contained in the Xilinx XC1765D serial conﬁguration

ROM (AlphaPC64.3). The code is executed by the 21064A on power-up as

described in Section 3.10. The serial ROM code initializes the system, which

includes loading debug monitor or other code from the ﬂash ROM. The serial

ROM code then transfers control to the code loaded from the ﬂash ROM.

The mini-debugger is also resident in the SROM. A jumper can be set in J3

to trap to the mini-debugger. Connector J2 provides a terminal port for the

mini-debugger.

Functional Description 3–41