User`s guide

Refer to the Intel Flash Memory document for additional information about
pin assignments and signal descriptions, register descriptions, and a functional
description (including timing, electrical characteristics, and mechanical data).
3.9.5 ISA Expansion Slots
Three ISA expansion slots are provided for plug-in ISA peripherals. One of the
slots is shared with the PCI and can be used for a PCI or ISA device.
3.10 Serial ROM
The 21064A uses a serial ROM (SROM) for its initialization code. When reset
is deasserted, the contents of the SROM are read into the Icache of the 21064A.
The code is then executed from the Icache. The general steps performed by the
SROM initialization are:
1. Initialize the CPU’s internal processor registers (IPRs).
2. Perform the minimum I/O subsystem initialization necessary to access the
real-time clock (RTC) and the system ROM (also called flash ROM).
3. Detect CPU speed by polling the periodic interrupt flag (PIF) in the RTC.
4. Set up memory and/or L2 cache parameters based on the speed of the CPU.
5. Wake up the DRAMs.
6. Initialize the L2 cache.
7. Copy the contents of the entire memory to itself to ensure good memory
data parity.
8. Scan system ROM for the special header that specifies where and how
system ROM firmware should be loaded.
9. Copy the contents of the system ROM to memory and begin code execution.
10. Pass parameters up to the next level of firmware to provide a predictable
firmware interface.
Figure 3–14 is a simplified block diagram of the SROM serial port logic.
The multiplex function for SROM signal real_srom_d and serial port signal
test_srom_d is performed by IRQ_T1_MACH210A (AlphaPC64.34) to gain an
SROM data input to the 21064A.
3–38 Functional Description