User`s guide
A.2.10 Host Address Extension Register 2 . ................... A–35
A.2.11 PCI Master Latency Timer Register. ................... A–36
A.2.12 TLB Tag Registers 0 Through 7 ....................... A–37
A.2.13 TLB Data Registers 0 Through 7 . . . ................... A–38
A.2.14 Translation Buffer Invalidate All Register ............... A–38
B SROM Initialization
B.1 SROM Initialization ................................... B–1
B.1.1 Firmware Interface ................................ B–2
B.1.2 Automatic CPU Speed Detection . . . ................... B–4
B.1.3 CPU Bus Interface Timing ........................... B–4
B.1.4 L2 Cache Read and Write Calculations ................. B–6
B.1.5 Memory Initialization . . . ........................... B–8
B.1.6 L2 Cache Initialization. . . ........................... B–9
B.1.7 Flash ROM (System ROM)........................... B–10
B.1.7.1 Special Flash ROM Headers . . . ................... B–10
B.1.7.2 Flash ROM Structure. ........................... B–12
B.1.7.3 Flash ROM Access . . . ........................... B–15
B.1.8 Icache Flush Code ................................. B–16
B.1.9 AlphaPC64 Configuration Jumpers . ................... B–16
C PCI Address Maps
C.1 PCI Interrupt Acknowledge/Special Cycle Address Space ...... C–1
C.2 PCI Sparse I/O Address Space ........................... C–1
C.3 SIO PCI-to-ISA Bridge Operating Register Address Space . . . . . C–1
C.4 PCI Configuration Address Space ........................ C–5
C.5 SIO PCI-to-ISA Bridge Configuration Address Space .......... C–6
C.6 PCI Sparse Memory Address Space ....................... C–7
C.7 PCI Dense Memory Address Space ....................... C–7
C.8 PC87312 Combination Controller Register Address Space ...... C–7
C.9 Utility Bus Device Address . . ........................... C–10
C.10 Interrupt Control PLD Addresses ........................ C–12
C.11 8242PC Keyboard and Mouse Controller Addresses . .......... C–12
C.12 Time-of-Year Clock Device Addresses . . . ................... C–12
C.13 Flash ROM.......................................... C–13
C.13.1 Flash Memory Segment Select Register ................. C–14
C.13.2 Flash Memory Addresses . ........................... C–14
C.13.3 Flash ROM Configuration Registers. ................... C–14
C.13.4 Flash ROM Memory Map. ........................... C–15
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