User`s guide

3.7 PCI Interrupts and Arbitration
The following subsections describe the PCI interrupt and arbitration (arbiter)
logic.
3.7.1 System Interrupts
Figure 3–11 shows the AlphaPC64 interrupt logic. Interrupt logic is
implemented in two programmable logic devices (PLDs), MACH210–20
and AMD22V10–25, shown on AlphaPC64.34. The PLDs allow each PCI and
Saturn IO (SIO) chip interrupt to be individually masked. The PLDs also allow
the current state of the interrupt lines to be read.
The AlphaPC64 has 17 PCI interrupts: four from each of the four PCI slots
(16) and one from the SIO bridge.
All PCI interrupts are combined in the PLD and drive a single output signal,
pci_isa_irq. This signal drives CPU input cpu_irq0 through a multiplexer.
There is also a memory controller error interrupt and an I/O controller error
interrupt within the CPU.
The CPU interrupt assignment, during normal operation, is listed in
Table 3–6.
Table 3–6 CPU Interrupt Assignment
Interrupt
Source
CPU
Interrupt Description
pci_isa_irq cpu_irq0 Combined output of the interrupt PLD
rtc_irq_l cpu_irq1 Real-time clock interrupt from DS1287
nmi cpu_irq2 Nonmaskable interrupt from the SIO bridge
— cpu_irq3,
cpu_irq4
Not used; tied to ground (AlphaPC64.2)
sys_irq0 cpu_irq5 Hardware interrupt from the PCI host bridge
(21071-CA) (AlphaPC64.23)
3–30 Functional Description