User`s guide

U40 generates six 66-MHz clock signals, which are distributed as shown in
Table 3–3.
Table 3–3 Distribution of 66-MHz Clock Signals
Clock Signal Name Destination
clk1x2_dec1 21071-BA0 (AlphaPC64.20)
clk1x2_dec2 21071-BA1 (AlphaPC64.20)
clk1x2_dec3 21071-BA2 (AlphaPC64.21)
clk1x2_dec4 21071-BA3 (AlphaPC64.21)
clk1x2_com_epic 21071-DA (AlphaPC64.6, AlphaPC64.23)
U39 generates thirteen 33-MHz clock signals. These 33-MHz clock signals are
shifted 90 degrees. They are distributed as shown in Table 3–4.
Table 3–4 Distribution of 33-MHz Shifted Clock Signals
Clock Signal Name Destination
pciclk_slot<3:2> PCI slots 3 and 2 (AlphaPC64.24)
pciclk_slot<1:0> PCI slots 1 and 0 (AlphaPC64.25)
pciclk_sio Saturn IO chip (PCI-to-ISA bridge) (AlphaPC64.26)
pciclk_epic 21071-CA, (AlphaPC64.23)
clk2xref_dec1_dec2 21071-BA0 (AlphaPC64.20–21)
clk2xref_dec3_dec4 21071-BA2 (AlphaPC64.20–21)
clk2xref_com_epic 21071-DA (AlphaPC64.6, AlphaPC64.23)
clk2xref_pal L2 cache PALs (AlphaPC64.7)
3–28 Functional Description