User`s guide

Figure 3–9 Primary Clock Distribution Network
LJ-04456.AI5
74FCT
805CT
pciclk_epic
clk1_pal
clk1_fb
AMCC
S4402
21064A
Buffer 2
Buffer 1
sysclk_pll90
sysclkout1
sysclk_pll0
U39
sysclk_pll0
sysclk_pll0_2x
U37
clk2xref_com_epic
clk2xref_dec3_dec4
clk2xref_dec1_dec2
clk2xref_pal
33-MHz Clocks
(Shifted 90°)
74FCT
805CT
Buffer 2
Buffer 1
sysclk_pll0_2x
sysclk_pll90
U38
clk1x2_com_epic
clk1x2_dec<1:4>
pciclk_sio
pciclk_slot<3:0>
66-MHz Clocks
33-MHz Clock to L2 Cache PAL
33-MHz Feedback Clock for S4402
33-MHz Clocks
(Shifted 90°)
Functional Description 3–27