User`s guide

Assume a TriQuint 500-MHz differential clock is supplied to the CPU. The
CPU divides the clock by 2, generating its internal clock operating at 250 MHz.
The internal clock is further divided by the CPU to generate the system clock
(sysclkout1). The system clock divisor can be programmed over a range from
2 to 17 as specified in Table 3–2.
Table 3–2 Clock Divisor Range (21064A)
J3-1
sysclkdiv_h
J3-3
jmp_irq2
J3-5
jmp_irq1
J3-7
jmp_irq0 Divisor
In
1
In In In 2
In In In Out
2
3
In In Out In 4
In In Out Out 5
In Out In In 6
In Out In Out 7
In Out Out In 8
In Out Out Out 9 (default)
Out In In In 10
Out In In Out 11
Out In Out In 12
Out In Out Out 13
Out Out In In 14
Out Out In Out 15
Out Out Out In 16
Out Out Out Out 17
1
Jumper in (logical 0)
2
Jumper out (logical 1)
Note
For other clocks generated by the CPU and not used on the board,
refer to the Alpha 21064 and Alpha 21064A Microprocessors Hardware
Reference Manual.
Functional Description 3–25