User`s guide

3.6 Clock Subsystem
The system clocks can be divided into three areas: the input clocks required
by the CPU, CPU clock distribution to the system logic, and miscellaneous
oscillators and clocks required for the peripheral interfaces and functions.
The 21064A CPU clock input is provided by a TriQuint phase-locked loop (PLL)
clock oscillator.
3.6.1 TriQuint PLL Clock Oscillator
As shown in Figure 3–8, the TriQuint PLL clock oscillator is composed of two
stages: oscillator and frequency multiplier, with the multiplier producing the
CPU clock input (clkin_h and clkin_h). Depending on the PLL clock part
selected (listed in Table 3–1), the oscillator stages can operate from 25 MHz to
50 MHz, with the multiplier stages producing output frequencies of 250 MHz
to 700 MHz.
Figure 3–8 TriQuint Clock Generator
LJ04137A.AI
TriQuint PLL Clock
Oscillator Stage
Frequency
Multiplier Stage
TriQuint PLL Clock
Oscillator
21064A
clkin_h
clkin_l
sysclkout1
AlphaPC64.3 AlphaPC64.2
Table 3–1 TriQuint Operating Frequencies
PLL Part Operating Frequencies
TQ2059 Oscillator running from 25 MHz to 35 MHz, X10 multiplier output from
250 MHz to 350 MHz
TQ2060 Oscillator running from 35 MHz to 50 MHz, X10 multiplier output from
350 MHz to 500 MHz
TQ2061 Oscillator running from 25 MHz to 35 MHz, X20 multiplier output from
500 MHz to 700 MHz
3–24 Functional Description