User`s guide

4.1.7 PCI Configuration Space (1 E000 0000 to 1 FFFF FFFF) . . . 4–12
4.1.7.1 PCI Configuration Cycles to Primary Bus Targets ...... 4–14
4.1.7.2 PCI Configuration Cycles to Secondary Bus Targets .... 4–14
4.1.8 PCI Sparse Memory Space (2 0000 0000 to
2 FFFF FFFF) .................................... 4–15
4.1.9 PCI Dense Memory Space (3 0000 0000 to 3 FFFF FFFF) . . . 4–18
4.2 PCI-to-Physical Memory Addressing ...................... 4–19
5 Board Requirements and Parameters
5.1 Power Requirements . . ................................ 5–1
5.2 Environmental Characteristics. . . ........................ 5–2
5.3 Physical Board Parameters ............................. 5–2
A System Register Descriptions
A.1 DECchip 21071-CA CSR Descriptions ..................... A–1
A.1.1 General Control Register ............................ A–1
A.1.2 Error and Diagnostic Status Register . . ................ A–4
A.1.3 Tag Enable Register ................................ A–6
A.1.4 Error Low Address Register . . ........................ A–8
A.1.5 Error High Address Register . ........................ A–8
A.1.6 LDx_L Low Address Register . ........................ A–9
A.1.7 LDx_L High Address Register ........................ A–9
A.1.8 Memory Control Registers . . . ........................ A–10
A.1.8.1 Video Frame Pointer Register ..................... A–10
A.1.8.2 Presence Detect Low-Data Register . ................ A–11
A.1.8.3 Presence Detect High-Data Register ................ A–12
A.1.8.4 Base Address Registers . . ........................ A–12
A.1.8.5 Configuration Registers . . ........................ A–13
A.1.8.6 Bank Set Timing Registers A and B ................ A–17
A.1.8.7 Global Timing Register . . ........................ A–22
A.1.8.8 Refresh Timing Register . ........................ A–23
A.2 DECchip 21071-DA CSR Descriptions ..................... A–24
A.2.1 Dummy Registers 1 Through 3 ....................... A–24
A.2.2 Diagnostic Control and Status Register . ................ A–25
A.2.3 sysBus Error Address Register ....................... A–29
A.2.4 PCI Error Address Register . . ........................ A–30
A.2.5 Translated Base Registers 1 and 2 ..................... A–31
A.2.6 PCI Base Registers 1 and 2 . . ........................ A–32
A.2.7 PCI Mask Registers 1 and 2 . ........................ A–33
A.2.8 Host Address Extension Register 0 .................... A–34
A.2.9 Host Address Extension Register 1 .................... A–34
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