User`s guide

3.5 Error Handling
The first error causes CSR error bits and the associated error address register
to be set and locked. If another error occurs, only the lost error bit is set and
int_hw0 is asserted to interrupt the processor. The int_hw0 signal is held
asserted as long as the corresponding error bit is set.
The PCI error address register (PEAR) logs addresses sent out or received on
the PCI. The sysBus error address register (SEAR) logs the address that was
sent out or received on the sysBus.
The 21071-DA returns a hard error condition in the iocmd<2:0> field on I/O
read transactions with errors. No interrupt is asserted in this case because
the 21064A has been notified that the read transaction had an error. There
is no case where the 21071-DA returns a soft error condition on an I/O read
transaction.
I/O write transactions are acknowledged with OK (
2
on cack<2:0>) because
of the write-and-run feature for I/O write transactions in the 21071-DA. The
transaction is acknowledged on the sysBus before it is initiated on the PCI.
Interrupt int is asserted to notify the 21064A that an error has occurred on
the PCI during the I/O write transaction.
All DMA transaction errors are flagged by interrupting the processor with int
when the error occurs.
Functional Description 3–23