User`s guide

3.4.7 DMA Write Buffer
The DMA write buffer has four entries. Each entry contains four longwords for
each 21071-BA and corresponding byte masks. However, only half the storage
for each entry is used. The extra storage is not accessible.
The DMA write buffer is loaded by the 21071-DA and is unloaded by the
21071-CA during a DMA write transaction on the sysBus. The byte masks are
used to merge the valid bytes of data written in the DMA write buffer with the
background data from the cache line, which may be obtained from the L2 cache
or memory.
3.4.8 Memory Write Buffer
The memory write buffer has four entries. Each entry contains four longwords
of data for each 21071-BA along with the corresponding parity bits. The
memory write buffer is loaded by the 21071-CA sysBus interface and is
unloaded by the 21071-CA memory controller.
3.4.9 Error Checking
The 21071-BA performs error checking on DMA transactions. When memory
or L2 cache data is read because of a DMA transaction (a DMA read or a
DMA-masked write transaction), the data is checked for parity errors.
If the data contains a parity error, the 21071-DA is notified (for a DMA read
transaction), or bad parity is written back into memory (for a DMA write
transaction).
In case of a DMA-masked write transaction, parity is generated for the merged
data going into the memory write buffer.
3.4.10 epiBus Data Path
The epiBus may be used to load the I/O read buffer or the DMA write buffer.
In addition to write data, byte masks are stored in the DMA write buffer.
The epiBus may also be used to unload the DMA read buffer (which also serves
as the I/O write buffer).
3.4.11 sysBus Output Selectors
Two levels of multiplexers select the output for the sysData bus. The first level
selects the source for each longword of data and parity bits. The second level
selects the two longwords to be driven on the sysData bus.
3–22 Functional Description