User`s guide

3.4 21071-BA Functional Overview
This section describes the data bus configurations and provides a functional
overview of the 21071-BA. Figure 3–7 shows a block diagram of the 21071-BA.
Figure 3–7 DECchip 21071-BA Block Diagram
LJ03948A.AI
PAD
Latch
sysData
<127:0>
DMA
Write
Buffer
Memory
Write
Buffer
memData
<127:0>
Merge
I/O
Read
Buffer
Memory
Read
Buffer
Parity
Generator
DMA
Read
Buffer
I/O
Write
Buffer
epiData <31:0>
75%
Parity
Check
3.4.1 sysData Bus
With the 21072-AA configuration, only the lower 32 bits of the sysData bus are
used:
• 21071-BA0 connects to data<31:0> (longword 0)
• 21071-BA1 connects to data<63:32> (longword 1)
• 21071-BA2 connects to data<95:64> (longword 2)
• 21071-BA3 connects to data<127:96> (longword 3)
3–20 Functional Description