User`s guide

The 21071-DA also supports PCI bus parking during reset. If the iogrant
signal is asserted by the PCI arbiter (req_l is always tristated by the 21071-DA
during reset), the 21071-DA will drive ad<31:0>, cbe<3:0>, and (one clock
cycle later) par. When iogrant is deasserted, the 21071-DA tristates these
signals.
3.3.2.9 PCI Retry Timeout
The 21071-DA implements a timeout mechanism to terminate CPU-initiated
transactions that do not complete on the PCI because of too many disconnects
or retries. When it initiates a CPU transaction on the PCI, the 21071-DA
counts the number of times it is retried or disconnected. If the number exceeds
2
24
, it flags an error to the CPU and aborts the transaction.
3.3.2.10 PCI Master Timeout
The PCI protocol specifies a mechanism to limit the duration of a master’s
burst sequence. The mechanism requires a PCI master to implement a latency
timer that counts the number of cycles since the assertion of frame#. If the
master latency timer has expired and the master’s grant has been taken away,
the master is required to surrender the bus.
This mechanism is intended to prevent masters from holding bus ownership for
extended periods of time, and selects low latency in instead of high throughput.
The 21071-DA implements a programmable master latency timer.
3.3.2.11 Address Stepping in Configuration Cycles
To provide flexibility and reduce design complexity when using the address-
stepping feature, the 21071-DA performs address stepping on configuration
read and write transactions. For these transactions, the 21071-DA will drive
the PCI bus for two clock cycles during the address phase for the idsel# pins
of all PCI devices to reach a valid logic level. The 21071-DA does not perform
address or data stepping in any other case.
3.3.2.12 Data Coherency
There are generally two agents in the system where data transfer actions must
be synchronized: CPU and a remote PCI device. The 21071-DA maintains
data coherency and synchronization between the agents by using the following
mechanisms:
• The 21071-DA preserves strict ordering of DMA write transactions initiated
on the PCI.
• DMA read transactions can bypass write transactions that are not to the
same address (double cache line). Strict ordering is maintained between
read and write transactions to the same address.
Functional Description 3–17