User`s guide

3.3.2.5 PCI Burst Order
PCI address bits ad<1:0> specify the burst ordering requested by the master
during memory transactions. When the 21071-DA is a master of the PCI, it
will always indicate a linear incrementing burst order (ad<1:0> = 0) on read
and write transactions.
On DMA transactions, the 21071-DA supports burst transfers only when a
linear-incrementing burst order is specified. If the master specifies a different
burst order (ad<1:0> is nonzero), the PCI interface disconnects the transaction
after one data transfer.
3.3.2.6 PCI Parity Support
The 21071-DA complies with the specification that all PCI devices generate
parity across PCI ad<31:0> (data and address lines) and cbe#<3:0> (command
and byte enables). When it is master of the PCI, it also checks the incoming
parity on I/O read transactions, interrupt vector read transactions, and
configuration read transactions during data phases. When the 21071-DA is
a target on the PCI, it checks parity during the address phase and during data
phases on memory write transactions.
3.3.2.7 PCI Exclusive Access
The 21071-DA supports the PCI Exclusive Access protocol, using the lock_l
signal. A locked transaction to main memory on the PCI causes the PCI
interface to lock out all nonexclusive main memory accesses initiated by PCI
masters. This is done by disconnecting the PCI transaction without completing
any data transfers. Until the lock is cleared on the PCI, only the PCI master
that locked main memory is allowed to complete transactions to main memory
(see the PCI Local Bus Specification).
On the sysBus side, the PCI lock causes the system lock flag to be cleared
by using the ioclrlock command encoded on the iocmd<2:0>. The system
lock flag is held cleared until all locked DMA read and write transactions to
memory have been completed on the sysBus and the lock is cleared on the PCI.
As a master on the PCI, the 21071-DA does not initiate locked transactions.
3.3.2.8 PCI Bus Parking
When no devices are requesting bus mastership, Digital recommends that the
system arbiter grant default bus ownership to the 21071-DA by asserting its
iogrant signal. This will reduce the latency for CPU-initiated transfers to the
PCI when the bus is idle. Granting the PCI to a device when no requests are
pending is referred to as bus parking in the PCI Local Bus Specification.If
the 21071-DA is granted the bus when it is not requesting the PCI, it will drive
the ad<31:0>, cbe_l<3:0>, and par signals.
3–16 Functional Description