User`s guide

3.3.2.2 DMA Write Buffer
The PCI interface has a write buffer for buffering DMA write data. The DMA
write buffer is made up of four entries. Each entry contains the cache-line
address, eight longwords of data, the byte enables corresponding to each
longword, and a valid bit for the entry. The untranslated PCI address is stored
in the DMA write buffer. Address translation is performed when the particular
entry is unloaded from the DMA write buffer. The address and valid bits are
stored in the 21071-DA, and corresponding data and byte enables are stored in
the 21071-BA.
3.3.2.3 DMA Read Buffer
The 21071-DA controls the DMA read buffer located in the 21071-BA. The
buffer stores up to 16 longwords of data organized as two cache lines. A
valid bit is implemented with each longword. Data received from the sysBus
(memory or cache) is loaded into the DMA read buffer by the sysBus interface,
and the corresponding valid bit is set. The data is unloaded by the PCI
interface.
3.3.2.4 PCI Burst Length and Prefetching
The PCI interface supports a maximum burst length of 16 longwords on
PCI write transactions directed toward main memory. If the PCI write
transaction starts on an even cache-line boundary with PCI (ad<5> = 0 and
PCI ad<4:2> = 0), a full burst of 16 longwords is supported. The transaction
will be terminated using a PCI disconnect after the sixteenth longword
has been received. In all other cases, the actual burst will be less than 16
longwords.
On DMA read transactions, a maximum burst length of eight longwords is
supported if DMA prefetching is not enabled in the 21071-DA and if a PCI
read multiple command was not used by the requesting device. A maximum
burst length of 16 longwords is supported if DMA prefetching is enabled in
the 21071-DA or if a PCI read multiple command was used by the requesting
device.
On CPU-initiated read transactions, when the 21071-DA is a master on the
PCI, a maximum burst length of two is supported.
On CPU-initiated write transactions, when the 21071-DA is a master on the
PCI, a maximum burst length of two is supported in sparse memory and I/O
spaces, and a maximum burst length of eight is supported in dense memory
space.
Functional Description 3–15