User`s guide

3.3.1 sysBus Interface

The sysBus interface includes the sysBus control state machine, the address

decode for CPU-initiated transactions, buffering for CPU-initiated transactions,

and the 21071-DA control and status registers.

3.3.1.1 Address Decode

The 21071-DA provides logic for translating and extending between the

21064A 34-bit physical address space and the 32-bit PCI address space. The

address decode in the 21071-DA uses the address mapping and translation

scheme described in Chapter 4 to generate PCI addresses on CPU-initiated

transactions. All systems using the 21071-DA are required to follow this

address mapping scheme.

3.3.1.2 I/O Write Transaction Buffering

The 21071-DA supports write-and-run I/O write transactions (see the PCI

Local Bus Speciﬁcation) and implements a 1-entry write buffer. The address

and control mechanism is in the 21071-DA; the corresponding data is stored in

the 21071-BA.

3.3.1.3 I/O Read Data Buffering

The 21071-DA provides data buffering for one I/O read transaction initiated by

the CPU. The I/O read buffer resides in the 21071-BA, but is controlled by the

21071-DA. The I/O read buffer is a temporary holding buffer and is invalidated

at the end of each I/O read transaction.

3.3.1.4 Wrapping Mode

The 21071-DA supports wrapped mode only on transactions initiated by the

21064A. The requested quadword is the only one that is returned on I/O read

transactions. To function correctly, the CPU must be conﬁgured in wrap mode.

3.3.2 PCI Interface

The PCI interface of the 21071-DA is a fully compliant PCI host bridge. It

acts as a master on the PCI on CPU-initiated transactions and is a target on

memory space transactions initiated by PCI masters.

3.3.2.1 DMA Address Translation

The PCI interface supports direct and scatter-gather mapping from the 32-bit

PCI address to the 34-bit physical address space. It provides two windows

that can be mapped to regions within the PCI address space. Each address

region can be independently programmed to be direct mapped or scatter-gather

mapped.

3–14 Functional Description