User`s guide

3.4.7 DMA Write Buffer ................................. 3–22
3.4.8 Memory Write Buffer ............................... 3–22
3.4.9 Error Checking ................................... 3–22
3.4.10 epiBus Data Path.................................. 3–22
3.4.11 sysBus Output Selectors . ........................... 3–22
3.5 Error Handling . . . ................................... 3–23
3.6 Clock Subsystem . . ................................... 3–24
3.6.1 TriQuint PLL Clock Oscillator ........................ 3–24
3.6.2 System Clock Distribution ........................... 3–26
3.7 PCI Interrupts and Arbitration .......................... 3–30
3.7.1 System Interrupts ................................. 3–30
3.7.2 PCI/ISA Arbitration ................................ 3–33
3.8 PCI Devices ......................................... 3–34
3.8.1 Intel Saturn IO Chip ............................... 3–34
3.8.2 PCI Expansion Slots ............................... 3–34
3.8.3 PCI Graphics Interface . . ........................... 3–34
3.9 ISA Devices ......................................... 3–35
3.9.1 Keyboard and Mouse Controller ....................... 3–35
3.9.2 Combination Controller . . ........................... 3–36
3.9.3 Time-of-Year Clock ................................. 3–37
3.9.4 Utility Bus Memory Devices ......................... 3–37
3.9.5 ISA Expansion Slots ............................... 3–38
3.10 Serial ROM ......................................... 3–38
3.11 dc Power Distribution ................................. 3–39
3.12 Reset and Initialization ................................ 3–41
3.13 System Software . . ................................... 3–41
3.13.1 Serial ROM Code .................................. 3–41
3.13.2 Flash ROM Code .................................. 3–43
3.13.3 Operating Systems ................................. 3–43
4 System Address Mapping
4.1 CPU Address Mapping to PCI Space . . . ................... 4–1
4.1.1 Cacheable Memory Space (0 0000 0000 to 0 FFFF FFFF) . . . 4–4
4.1.2 Noncacheable Memory Space (1 0000 0000 to
1 7FFF FFFF) . ................................... 4–4
4.1.3 DECchip 21071-CA CSR Space (1 8000 0000 to
1 9FFF FFFF) . ................................... 4–5
4.1.4 DECchip 21071-DA CSR Space (1 A000 0000 to
1 AFFF FFFF) . ................................... 4–7
4.1.5 PCI Interrupt Acknowledge/Special Cycle Space
(1 B000 0000 to 1 BFFF FFFF) ....................... 4–8
4.1.6 PCI Sparse I/O Space (1 C000 0000 to 1 DFFF FFFF)...... 4–9
v