User`s guide

3.2.2.5 Transaction Scheduler
The memory interface does memory refresh, cache-line read and write
transactions, and shift register loads to VRAM bank set 8. The memory
controller has a scheduler that prioritizes transactions and selects one to be
serviced. If the selected transaction is waiting for row address strobe (RAS)
precharge, and another higher priority transaction is initiated, the scheduler
deselects the previously chosen transaction and selects the higher priority
transaction.
3.2.2.6 Programmable Memory Timing
The memory control state machine performs its sequence of steps through
all memory transactions. On memory read and write transactions, it
communicates with the 21071-BA chips so that data may be latched from
the memData bus or driven onto the memData bus respectively.
The memory control state machine is actually two state machines (master,
and read and write). The master state machine performs the RAS and
column address strobe (CAS) assertions, and controls when the other state
machine starts. The read and write state machine performs the sequencing
for generating the memcmd to read or write memory data. The read and
write state machine is started by the master and runs through its sequence
independently.
3.2.2.7 Presence Detect Logic
The 21071-CA supports loading the status of 32 presence pins into a register
after reset. The 32 bits are loaded into a shift register on the module and then
are shifted 1 bit at a time into the 21071-CA.
3–12 Functional Description