User`s guide

3.2.2 Memory Controller
This section summarizes memory organization and memory controller features.
3.2.2.1 Memory Organization
The 21071-CA supports up to:
• Eight bank sets of DRAM (bank sets 0..7), where one bank set equals four
SIMMs
• One bank set (bank set 8) of VRAM
Each bank set can be made up of one or two banks. A bank of memory refers
to one width of DRAMs, implemented with SIMMs. The SIMM implementation
requires more than one SIMM to form one memory bank. For example, four
33-bit SIMMs are required to form the 128-bit bank width. On the AlphaPC64,
the 21071-CA supports 16MB to 512MB of DRAM.
Memory is accessed at 128 bits. Because the AlphaPC64 uses longword parity,
132 bits are required.
3.2.2.2 Memory Address Generation
The programmable base address of a bank set must be aligned to the natural
size boundary. For example, an 8MB bank set must start on an 8MB boundary.
The hardware allows for holes in memory with badly programmed addresses.
Each bank set has a programmable base address and size. The incoming
physical address is compared in parallel with the memory ranges of all bank
sets present. Depending on the size of the bank set, a variable number of
physical address and base address bits from the CSR are compared.
3.2.2.3 Memory Page Mode Support
The 21071-CA supports page mode optimization on the memory banks within a
transaction. Page mode between transactions is supported on DMA read burst
transactions and on memory write transactions.
3.2.2.4 Read Latency Minimization
To minimize the read latency seen by devices on the sysBus, the memory
controller performs certain optimizations in the way transactions are selected.
In general, because write transactions can go into a deep write buffer, read
transactions are given priority over write transactions (that is, to the extent
that in some cases the memory controller waits for a read transaction to
execute even if there are write transactions queued in the write buffer).
Functional Description 3–11