User`s guide

3.2.1.3 sysBus Control
The sysBus controller consists of a sequencer that receives CPU and DMA
command fields for decode, results from the sysBus arbiter logic, and status
from the memory controller logic. The sequencer supplies machine state
signals that are used to generate L2 cache control and read requests to the
memory controller; to load data from the sysBus into the read, merge, and
write buffers; and to acknowledge cycles to the CPU and 21071-DA. The
sysBus controller supports wrapping on the sysBus.
3.2.1.4 Address Decoding
The 21071-CA sysBus interface logic decodes the sysBus address for both CPU
and DMA requests to determine the action to take. It supports cacheable and
noncacheable memory accesses, as well as accesses to its CSR space. (See
Chapter 4 for information about address space mapping.)
3.2.1.5 Error Handling
During CPU and DMA transactions, the 21071-CA detects the following errors:
• L2 cache tag address parity error
• L2 cache tag control parity error
• Nonexistent memory error
When one or more errors are detected on a transaction, the 21071-CA signals
the errors to the CPU or the 21071-DA at the end of the transaction by
acknowledging a hard error condition on the cack<2:0> or iocack<1:0> signal
lines. The current sysadr<33:5> is logged in the error address register, and
error status logged in the CPU clears all the error status bits by writing the
control and status register (CSR).
If errors occur on a transaction while the error address and status are locked,
the transaction is acknowledged with a hard error condition on the cack<2:0>
or iocack<1:0> fields. The LOSTERR bit in the error and diagnostics status
register is set, and the lost error address and status are not recorded.
The hard error condition overrides STx_C transaction fail. The lock bit is
UNPREDICTABLE after LDx_L transactions with errors.
3–10 Functional Description