User`s guide

3.2.1.1 sysBus Arbitration
The 21071-CA arbitrates between the CPU and 21071-DA, which requests use
of the sysBus and the L2 cache when they have a transaction to perform. The
CPU has default ownership of the sysBus so that it can access the L2 cache
whenever the 21071-DA is not requesting the bus.
3.2.1.2 L2 Cache Control
Figure 3–5 shows the implementation of a cache subsystem with an 8MB
cache. Note that the 21071-CA supports a 128-bit secondary cache interface.
Figure 3–5 Cache Subsystem for an 8MB Cache
LJ-04136.AI
AlphaPC64 L2 Cache SIMMs (8MB)
Cache/Memory
Control
21071-CA
CPU
128-Bit Data
CPU Cache Control
Tag, Tag V, D, P
Address
System
Cache
Control
Data Path
21071-BA
PAL
Arrays
21071-DA
FCT162244ET
AlphaPC64.2
AlphaPC64.20-21
AlphaPC64.7
AlphaPC64.7
AlphaPC64.10
The L2 cache controller provides control for the secondary cache on CPU-
initiated memory read and write transactions that miss, and on all CPU-
initiated memory LDx_L and STx_C transactions (hits and misses).
On DMA-initiated transactions, the L2 cache controller provides control for
probing the cache and extracting or invalidating the cache line when required.
The 21071-CA supports a write-back cache.
Functional Description 3–9