User`s guide

3.2 21071-CA Functional Overview
The 21071-CA (AlphaPC64.6) provides second-level cache and memory control
functions. It also controls the cache and memory data path located on the
21071-BA. Figure 3–4 shows a block diagram of the 21071-CA.
Figure 3–4 21071-CA Block Diagram
LJ-04135.AI
Tag
Compare
Address
Generation
tagadr<31:17>
adr<33:5>
Write
Buffer
Address
Row and
Column
Generation
Memory
Control
Memory
Bank
Generation
Write Address
Write Bank
Read Bank
Read Address
b<3:0>_ras<1:0>b_l
AlphaPC64.12-14
SysBus
and
L2 Cache
Control
Dath Path Control
L2 Cache Control
SysBus Control
8
b<1:0>_cas<3:0>b_l
8
b<3:0>_ras<1:0>_l
8
b0<3:0>_we_l
4
b<3:0>_we_l
4
b0<3:0>_adr<11:0>
48
AlphaPC64.6
AlphaPC64.6
AlphaPC64.7
AlphaPC64.6
AlphaPC64.6
AlphaPC64.15
3.2.1 sysBus Interface
The CPU, 21071-DA (AlphaPC64.26), cache, and 21071-CA communicate with
each other through the sysBus. The sysBus is essentially the processor pin
bus with additional signals for DMA transaction control, arbitration, and cache
control.
3–8 Functional Description