User`s guide

3.1.3 21071-BA Introduction
The 21071-BA chip provides a 32-bit data path from the 21064A to main
memory and I/O. Four chips are required for the 128-bit interface.
The chip contains the cache and memory interface data path, which includes
buffers for victim, noncacheable write, and DMA write operations. It also
contains the I/O subsystem data path, which provides buffering for DMA read
and write data, and I/O read and write data.
The chip interfaces to the cache and CPU by using the CPU sysBus (pin bus).
It interfaces with the 21071-DA through the 32-bit epiBus (communications
path between the 21071-DA and 21071-BA). The 21071-BA functions as the
data path for the cache, memory, and I/O subsystem, and contains the following
data path functions:
Error Detection Logic—The 21071-BA supports longword parity on the
128-bit memory interface. Error checking and generation is performed only on
DMA-initiated transactions; error checking and generation on CPU-initiated
transactions is performed by the CPU.
Memory Write Buffer—The memory write buffer has four entries; each entry
is a cache line (32B). The buffer is distributed across the four 21071-BA chips
in the system. Data stored in this buffer has passed all cache coherency checks
and is written to memory in the order it was received on the sysBus.
Memory Read Buffer—The memory read buffer is a one-cache-line temporary
holding buffer used to store data written by the CPU on memory write
transactions, or to store data read from the PCI bus on CPU read transactions.
I/O Write Buffer—The I/O write buffer has two entries. One entry acts as a
write buffer for CPU I/O write transactions to the 21071-BA or PCI bus; the
other acts as a holding buffer.
DMA Read Buffer—The DMA read buffer stores data that is being read from
the memory by a device on the PCI bus. This buffer consists of two cache lines
and is distributed across the 21071-BA chips.
DMA Write Buffer—The DMA write buffer stores four cache lines of PCI
memory write data. Each entry is unloaded after the necessary cache
coherency checks have been performed.
Functional Description 3–7