User`s guide

The following list summarizes the major features of the 21071-DA:
• Scatter-gather mapping from the 32-bit PCI address to the 34-bit physical
address, with an onchip, 8-entry translation lookaside buffer (TLB) for fast
address translations. To reduce cost, the scatter-gather tables are stored in
memory and are automatically read by the 21071-DA when a translation
misses in the TLB.
• Supports a maximum PCI burst length of 16 longwords on PCI memory
read and write transactions.
• Supports two types of addressing regions on CPU-initiated transactions to
PCI space.
Sparse space for accesses with byte and word granularities, and a
maximum burst length of two.
Dense space for burst lengths from one to eight write transactions and
a burst length of two on read transactions. This region can be used
for memory-like structures, such as frame buffers, which require high
bandwidth accesses.
• Stores address information for the DMA write buffer and controls the
loading of the DMA write buffer and I/O read buffer.
• Stores address information for the I/O write buffer and controls the
unloading of the I/O write buffer and DMA read buffer.
Note
The 21071-DA is not a PCI peripheral; it is a bridge between the
PCI peripherals and the CPU/system memory. The chip implements
functions of a host bridge that are not sufficient to interface the chip as
a PCI peripheral component.
3–6 Functional Description