User`s guide

Figure 3–2 Basic Cache and Memory Subsystem Address and Data Paths
LJ03944A.AI
21071-BA0
32 Bits
32 Bits
32 Bits
32 Bits
32 Bits
32 Bits
32 Bits
32 Bits
memData <127:0>
Memory Address and Control
sysData <127:0> Check <21, 14, 7, 0>
SysAdr
L2 Cache Ctrl
Tag Adr Ctrl
memPar <3:0>
21071-BA1 21071-BA2 21071-BA3
Memory
DRAMs
CPU
Cache
21071-CA
21071-DA Data Path Bit Assignments
memData LinessysData Lines
memData <31:0>21071-BA0 <31:0>
memData <63:32>21071-BA1 <63:32>
memData <95:64>21071-BA2 <95:64>
memData <127:96>21071-BA3 <127:96>
3.1.2 21071-DA Introduction
The 21071-DA chip functions as the bridge between the PCI and the CPU
and its L2 cache and memory (see Figure 3–3). The chip interface protocol is
compliant with the PCI local bus. With the exception of a few pipeline registers
and the parity tree, all the data path functions required to support the PCI
reside in the chip.
3–4 Functional Description