User`s guide

3.2.1 sysBus Interface. . . ................................ 3–8
3.2.1.1 sysBus Arbitration .............................. 3–9
3.2.1.2 L2 Cache Control ............................... 3–9
3.2.1.3 sysBus Control . ................................ 3–10
3.2.1.4 Address Decoding ............................... 3–10
3.2.1.5 Error Handling ................................ 3–10
3.2.2 Memory Controller . ................................ 3–11
3.2.2.1 Memory Organization . . . ........................ 3–11
3.2.2.2 Memory Address Generation ...................... 3–11
3.2.2.3 Memory Page Mode Support ...................... 3–11
3.2.2.4 Read Latency Minimization ....................... 3–11
3.2.2.5 Transaction Scheduler . . . ........................ 3–12
3.2.2.6 Programmable Memory Timing .................... 3–12
3.2.2.7 Presence Detect Logic . . . ........................ 3–12
3.3 21071-DA Functional Overview . . ........................ 3–13
3.3.1 sysBus Interface. . . ................................ 3–14
3.3.1.1 Address Decode ................................ 3–14
3.3.1.2 I/O Write Transaction Buffering .................... 3–14
3.3.1.3 I/O Read Data Buffering . ........................ 3–14
3.3.1.4 Wrapping Mode ................................ 3–14
3.3.2 PCI Interface ..................................... 3–14
3.3.2.1 DMA Address Translation ........................ 3–14
3.3.2.2 DMA Write Buffer .............................. 3–15
3.3.2.3 DMA Read Buffer .............................. 3–15
3.3.2.4 PCI Burst Length and Prefetching. . ................ 3–15
3.3.2.5 PCI Burst Order ............................... 3–16
3.3.2.6 PCI Parity Support ............................. 3–16
3.3.2.7 PCI Exclusive Access ............................ 3–16
3.3.2.8 PCI Bus Parking ............................... 3–16
3.3.2.9 PCI Retry Timeout .............................. 3–17
3.3.2.10 PCI Master Timeout ............................ 3–17
3.3.2.11 Address Stepping in Configuration Cycles ............ 3–17
3.3.2.12 Data Coherency ................................ 3–17
3.3.2.13 Deadlock Resolution ............................. 3–18
3.3.2.14 Guaranteed Access-Time Mode .................... 3–19
3.3.2.15 Interrupts .................................... 3–19
3.4 21071-BA Functional Overview . . ........................ 3–20
3.4.1 sysData Bus ...................................... 3–20
3.4.2 memData Bus .................................... 3–21
3.4.3 epiData Bus ...................................... 3–21
3.4.4 Memory Read Buffer ............................... 3–21
3.4.5 I/O Read Buffer and Merge Buffer ..................... 3–21
3.4.6 I/O Write Buffer and DMA Read Buffer . ................ 3–21
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