User`s guide

3.1.1 21071-CA Introduction
The 21071-CA chip provides the interface between the 21064A and main
memory. It provides the system interface to the cache. The chip controls and
moves data to and from banks of main memory. It responds to commands from
the CPU and 21071-DA and arbitrates between them. It also supports control
of the L2 cache RAMs during a CPU cache miss and direct memory access
(DMA) transactions.
On the AlphaPC64, the 21071-CA controls two banks of DRAM SIMMs.
The SIMMs can range in size from 1M x 36 to 16M x 36. Each bank can
accommodate four 36-bit SIMMs to support a 128-bit data path with longword
parity. Figure 3–1 shows the maximum and minimum SIMM bank layouts.
The chip provides support for a single video bank of dual-port RAM (VRAM).
This bank may have 128K, 256K, 512K, or 1M locations. Each location consists
of octaword data for the 128-bit interface. VRAM capacity can vary from 1MB
to 16MB.
The components of the cache and memory subsystem are distributed between
the 21071-CA and the 21071-BA. Together, the chips serve as an interface
between the sysBus and memory subsystem (see Figure 3–2).
The CPU, 21071-DA, cache, and memory communicate with each other
through the sysBus. The sysBus is essentially the processor pin bus with
additional signals for DMA transaction control, arbitration, and cache control.
The 21071-CA chip controls the L2 cache and memory. The following list
summarizes the major features of the 21071-CA:
• Provides control for filling the L2 cache and extracting victims on CPU-
initiated transactions.
• Provides control for probing the L2 cache on DMA transactions and
invalidating the L2 cache on DMA write hits.
• Arbitrates between the CPU and the 21071-DA for control of the sysBus.
• Stores addresses for the four-cache-line memory write buffer.
• Controls the loading of the I/O write buffer and the DMA read buffer.
• Uses fast-page mode on the DRAMs to improve performance on DMA burst
reads and memory write transactions.
3–2 Functional Description