User`s guide

3
Functional Description
This chapter describes the functional operation of the AlphaPC64.
The description introduces the ASIC support chipset and describes its
implementation with the 21064A microprocessor and its supporting memory
and I/O devices.
Information, such as bus timing and protocol, found in other specifications,
data sheets, and reference documentation is not duplicated. Appendix D
provides a list of supporting documents and order numbers.
Note
For detailed descriptions of chipset logic, operations, and transactions,
refer to the DECchip 21071 and DECchip 21072 Core Logic Chipsets
Data Sheet.
For details of the PCI interface, refer to the PCI System Design Guide
and the PCI Local Bus Specification.
3.1 Chipset Introduction
The DECchip 21072 chipset provides a cost-competitive solution for designers
developing uniprocessor systems using the 21064A microprocessor. The chipset
provides a 128-bit memory interface and includes the following three gate
arrays:
• DECchip 21071-CA (21071-CA): cache and memory controller—208-pin
plastic quad flat pack (PQFP)
• DECchip 21071-DA (21071-DA): PCI interface—208-pin PQFP
• DECchip 21071-BA (21071-BA): data path—208-pin PQFP
Functional Description 3–1