User`s guide

1.1.4 Level 2 Cache Subsystem Overview

The external Level 2 (L2) cache subsystem supports 512KB, 1MB, 2MB, 4MB,

or 8MB cache sizes by using a 128-bit data bus. The L2 cache size can be

reconﬁgured through onboard hardware and software jumpers.

The AlphaPC64 supports the L2 cache SIMM sizes shown in Table 1–1. Two

SIMMs are required per system. The AlphaPC64 comes with a 2MB, 12-ns L2

cache.

Table 1–1 L2 Cache SIMM Sizes

L2 Cache Size Static RAM (SRAM) Access Times

512KB 6 ns, 8 ns, 10 ns, 12 ns, 15 ns

1MB

, 2MB 6 ns, 8 ns, 10 ns, 12 ns, 15 ns

4MB

, 8MB 6 ns, 8 ns, 10 ns, 12 ns, 15 ns

Cache size can be reduced with jumpers.

1.1.5 Clock Subsystem Overview

The clock subsystem provides clocks to the 21072 chipset and PCI devices. Two

oscillators provide clocks for the ISA and combination chip functions.

1.1.6 PCI Interface Overview

The PCI interface provides a selectable PCI speed between 25 MHz and

33 MHz (based on 21064A clock divisors). An Intel 82378ZB Saturn IO (SIO)

chip provides a PCI-to-ISA bridge.

The PCI has three dedicated slots and one shared slot with the ISA.

1.1.7 ISA Interface Overview

The ISA provides an expansion bus and the following system support functions:

• Mouse and keyboard controller functions provided through an Intel 8242

chip

• National 87312 chip used as the combination chip providing a diskette

controller; two universal, asynchronous receiver/transmitters (UARTs); an

integrated device electronics (IDE) controller; a bidirectional parallel port;

and an interface to the utility bus (Ubus) for ISA interrupts and jumper

status

1–4 AlphaPC64 Introduction