User`s guide
1.1.1 Memory Subsystem
The DRAM memory can provide 16MB to 512MB with a 128-bit data bus. The
memory is contained in two banks of four commodity single inline memory
modules (SIMMs). Each SIMM is 36 bits wide, with 32 data bits, 1 parity bit,
and 3 unused bits with 70-ns or less access. The following SIMM sizes are
supported:
1Mx36 2Mx36 4Mx36 8Mx36 16Mx36
1.1.2 DECchip 21072 Support Chipset
The 21064A is supported by a DECchip 21072 ASIC chipset (21072), with a
128-bit memory interface. The chipset consists of the following three chips:
• DECchip 21071-CA (21071-CA) provides the interface from the CPU to
cache and main memory, and includes the cache and memory controller.
• DECchip 21071-BA (21071-BA) provides a 32-bit data path from the CPU
to memory and I/O. Four chips provide the 128-bit interface.
• DECchip 21071-DA (21071-DA) provides an interface from the CPU to the
PCI.
The chipset includes the majority of functions required to develop a high-
performance PC or workstation, requiring minimum discrete logic on the
module. It provides flexible and generic functions to allow its use in a wide
range of systems.
1.1.3 PAL Control Set
The AlphaPC64 contains a 4-PAL control set and includes the following:
• Two 16V8-5 PALs provide L2 cache output-enable and write-enable
functions.
• One 22V10-25 PAL provides interrupt address decode functions and utility
bus (Ubus) control.
• One MACH210-20 PAL provides the PCI and ISA interrupts.
1–2 AlphaPC64 Introduction