User`s guide

Memory controller, 3–11
memory address generation, 3–11
memory organization, 3–11
memory page mode support, 3–11
presence detect logic, 3–12
programmable memory timing, 3–12
read latency minimization, 3–11
transaction scheduler, 3–12
Memory figures, xv
Memory organization, 3–11
Memory page mode support, 3–11
Memory read buffer, 3–21
Memory subsystem, 1–2
Memory write buffer, 3–22
Must be zero, xv
N
Noncacheable memory space, 4–4
Numbering, xiv
O
Operating systems, 3–43
debug and monitor code, 3–43
serial ROM code, 3–41
software support, 1–5
system software, 3–41
Ordering products, D–2
P
PAL control set, 1–2
Parts
ordering, D–2
PC87312 register address map, C–7, C–8
PCI
arbitration, 3–30, 3–33
configuration address space, C–5
dense memory address space, C–7
input/output address space, C–1
interrupt acknowledge/special cycle
address space, C–1
sparse memory address space, C–7
PCI base register 1, A–32
PCI base register 2, A–32
PCI burst length and prefetching, 3–15
PCI burst order, 3–16
PCI bus parking, 3–16
PCI configuration space, 4–12
PCI dense memory space, 4–18
PCI devices, 3–34
Intel Saturn IO chip, 3–34
PCI expansion slots, 3–34
PCI graphics interface, 3–34
PCI error address register, A–30
PCI exclusive access, 3–16
PCI expansion slots, 3–34
PCI graphics interface, 3–34
PCI interface, 3–14
address stepping in configuration cycles,
3–17
DMA address translation, 3–14
DMA read buffer, 3–15
DMA write buffer, 3–15
PCI burst length and prefetching, 3–15
PCI burst order, 3–16
PCI bus parking, 3–16
PCI exclusive access, 3–16
PCI master timeout, 3–17
PCI parity support, 3–16
PCI retry timeout, 3–17
PCI interface overview, 1–4
PCI interrupt acknowledge/special cycle,
4–8
PCI interrupt logic, 3–30
PCI mask register 1, A–33
PCI mask register 2, A–33
PCI master latency timer register, A–36
PCI master timeout, 3–17
PCI parity support, 3–16
PCI retry timeout, 3–17
PCI sparse I/O space, 4–9
PCI sparse space, 4–15
PCI-to-physical memory addressing, 4–19
Peripheral component interconnect
See PCI
Index–4