User`s guide

F
Features, 1–1
Flash ROM, 3–43, B–10
access, B–15
address bit 19, B–15
banks, B–12
enable/disable jumpers, 2–6
header content, B–10
higher bank image selection, B–12
MAKEROM tool, B–10
operating systems, 3–43
special headers, B–10
structure, B–12
TOY RAM location 3F, B–13
update-enable jumper, B–15
G
General control register, A–1
Global timing register, A–22
Graphics interface, 3–34
Guaranteed access-time mode, 3–19
H
Handling errors with error address register
locked, 3–23
Hardware configuration jumpers, 2–5
Host address extension register 0, A–34
Host address extension register 1, A–34
Host address extension register 2, A–35
I
I/O read and merge buffer, 3–21
I/O read data buffering, 3–14
I/O space address map, C–1
I/O write and DMA read buffer, 3–21
I/O write transaction buffering, 3–14
IDE register address map, C–10
idsel pin select, C–5
Initialization, 3–41
Intel Saturn IO chip
See SIO chip
Interrupt control, 3–30
Interrupt control and PCI arbitration logic,
3–30
Interrupt mask registers, 3–33
Interrupt scheme, 3–30
Interrupts, 3–19
ISA arbitration, 3–33
ISA devices, 3–35
combination controller, 3–35, 3–36
ISA expansion slots, 3–38
time-of-year clock, 3–37
utility bus memory devices, 3–37
ISA expansion slots, 3–38
ISA interface overview, 1–4
L
L2 cache
control, 3–9
subsystem, 1–4
LDx_L high address register, A–9
LDx_L low address register, A–9
Level 2 cache
See L2 cache
Literature, D–3
M
memData bus, 3–21
Memory address generation, 3–11
Memory and register contents radix, xv
Memory control registers, A–10 to A–24
bank set timing register A, A–17
bank set timing register B, A–17
base address registers, A–12
configuration registers, A–13
global timing register, A–22
presence detect high-data register, A–12
presence detect low-data register, A–11
refresh timing register, A–23
video frame pointer register, A–10
Index–3