User`s guide

B
BA error checking, 3–22
Bank set timing register A, A–17
Bank set timing register B, A–17
Base address registers, A–12
Bit notation, xvii
Board configuration, 2–1
Board connectors, 2–6
Board layout, 1–6
Board overview, 1–1
Board uses, 1–6
Bridge
See SIO PCI-to-ISA bridge
C
CA error handling, 3–10
Cacheable memory space, 4–4
Cautions, xvii
Chipset overview, 3–1
DECchip 21071-BA, 3–7
DECchip 21071-CA, 3–2
DECchip 21071-DA, 3–4
Chipset support, 1–2
Clock subsystem, 3–24
14.3-MHz and 24-MHz clocks, 3–29
clock distribution, 3–26
system clock, 3–25
TriQuint PLL clock frequencies, 3–24
TriQuint PLL clock oscillator, 3–24
Clock subsystem overview, 1–4
Combination controller, 3–36
Components, 1–1
Configuration registers, A–13
CPU-to-PCI address space, 4–1
D
Data coherency, 3–17
Data units, xvii
dc power distribution, 3–39
See also Power requirements
Deadlock resolution, 3–18
Debug and monitor code
serial ROM code, 3–41
Debug and monitor ROM
system support, 1–5
DECchip 21071-BA chip
See 21071-BA
DECchip 21071-CA chip
See 21071-CA
DECchip 21071-DA chip
See 21071-DA
DECchip 21072 chipset
See Chipset overview
Design support, 1–6
Diagnostic control and status register, A–25
Digital Semiconductor Information Line,
D–1
DMA address translation, 3–14
DMA read buffer, 3–15
DMA write buffer, 3–15, 3–22
Document conventions, xiv
extents, xv
numbering, xiv
ranges, xv
Documentation, D–3
Dummy registers 1 through 3, A–24
E
Environmental characteristics, 5–2
epiBus data path, 3–22
epiData bus, 3–21
Error and diagnostic status register, A–4
Error handling, 3–23
Error high address register, A–8
Error low address register, A–8
Evaluation board uses, 1–6
Extents, xv
Index–2