User`s guide

Index
21071-BA
functional description, 3–20
BA error checking, 3–22
DMA write buffer, 3–22
epiData bus, 3–21
I/O read and merge buffer, 3–21
I/O write and DMA read buffer, 3–21
memData bus, 3–21
memory read buffer, 3–21
memory write buffer, 3–22
sysData bus, 3–20
overview, 3–7
21071-CA
CSR descriptions, A–1 to A–24
See also specific register entries
CSR space, 4–5
functional description, 3–8
address decoding, 3–10
CA error handling, 3–10
L2 cache control, 3–9
sysBus arbitration, 3–9
sysBus controller, 3–10
sysBus interface, 3–8
overview, 3–2
21071-DA
CSR descriptions, A–24 to A–38
See also specific register entries
CSR space, 4–7
functional description, 3–13
PCI interface, 3–14
sysBus interface, 3–14
overview, 3–4
A
Address decode, 3–14
Address decoding, 3–10
Address map
bridge
configuration registers, C–6
operating registers, C–1
IDE register, C–10
operating registers, C–1
PC87312 registers, C–7, C–8
physical, C–1
Saturn IO chip
configuration registers, C–6
operating registers, C–1
utility bus decode, C–10
Address radix, xv
Address space
PCI configuration, C–5
PCI dense memory, C–7
PCI I/O, C–1
PCI interrupt acknowledge/special cycle,
C–1
PCI sparse memory, C–7
Address stepping in configuration cycles,
3–17
Alpha documentation, D–3
AlphaPC64 introduction, 1–1
Arbitration
PCI, 3–30
scheme, 3–33
Associated literature, D–3
Index–1