User`s guide

Table C–12 Flash ROM Configuration Registers
Offset
Data Written
on First Access Register
X
1
FF Read array/reset register
X 90 Intelligent identifier register
X 70 Read status register
X 50 Clear status register
BA
2
20 Erase setup/confirm register
X B0 Erase suspend/resume register
WA
3
40 Byte write setup/write register
WA 10 Alternate byte write setup/write register
1
X = Any byte within the flash ROM address range.
2
BA = Target address within the block being erased.
3
WA = Target address of write transaction to memory.
All accesses to flash ROM (except for read transactions) require two bus cycles.
During the first cycle, register data is written to set up the registers. During
the second cycle, the read or write transaction performs the operation desired.
For more information about reading, erasing, and writing the flash ROM, see
the Intel Flash Memory document.
Accessing the flash ROM registers requires byte access, which is only possible
through use of PCI sparse memory space. The AlphaPC64 flash ROM resides
in PCI memory address range FFF8 0000 to FFFF FFFF. See Section 4.1.8 for
information about accessing this address range through sparse memory space.
C.13.4 Flash ROM Memory Map
There are eight blocks in each bank of flash ROM memory. Table C–13 lists
the address ranges of the blocks.
PCI Address Maps C–15